1. Field of the Invention
This invention relates to a multi-rate transmission apparatus which is ready for multi-rate transmission without varying a transmission processing rate even if a phase modulation system or a coding rate is varied.
2. Description of the Related Art
Phase modulation systems include a two-phase type phase modulation (phase-inversion modulation) system, a polyphase phase modulation system and an orthogonal amplitude modulation system. FIG. 8 illustrates relationships between codes and data of the modulation systems on a coordinate system represented by a real axis and an imaginary axis.
Referring to FIG. 8, reference numeral 800 denotes an example of BPSK (Binary Phase Shift Keying) which is a two-phase type modulation system, 801 an example of QPSK (Quadrature Phase Shift Keying) which is a polyphase phase modulation system, and 802 an example of 16QAM (16 Quadrature Amplitude Modulation) which is an orthogonal amplitude modulation system.
In BPSK, data is represented with “0” and “1” on the coordinate system, and a code corresponding to a point on the coordinate system is transmitted with a carrier. In QPSK which is a polyphase phase modulation system, data is represented with 2 bits called dibits, and a corresponding code is transmitted. Meanwhile, in the 16QAM of an orthogonal amplitude modulation system, data is represented with 4 bits.
In order to vary the phase modulation system, it is necessary to re-arrange and transmit data for each number of bits suitable for the modulation system.
As an apparatus for varying the modulation system or the coding rate, a variable coding rate error correction transmission apparatus is conventionally known and disclosed, for example, in Japanese Patent Laid-Open No. Hei 10-163883.
The transmission apparatus mentioned is illustrated at FIG. 9 and includes an input signal production apparatus 11, a parallel to serial converter 12, a convolution coding unit 13, a puncture circuit 14, a clock generation circuit 15, a clock sampling out circuit 16, a ½ frequency divider 17, and a ⅛ frequency divider 18.
In the transmission apparatus, parallel data DATAB outputted from the input signal production apparatus 11 is supplied to the parallel to serial converter 12, by which it is converted into another parallel data DATA.
The clock sampling out circuit 16 samples out n clocks CLK0 from m clocks CLK0 outputted from the clock generation circuit 15 based on a coding rate (m−n)/m to produce a data readout clock signal CLK.
The convolution coding unit 13 performs two kinds of convolution operation and outputs coded data CDATA1 and CDATA2 with error correction codes added thereto in synchronism with the clock signal CLK.
The puncture circuit 14 deletes data at predetermined positions from the parallel coded data in accordance with the coding rate and outputs transmission symbol data in synchronism with a symbol clock signal CLKS.
However, where the modulation system or the coding rate is varied with the conventional system, it is often the case that, if the data transfer rate increases, then the rate of a reference clock signal in the circuit is raised or a plurality of different clocks are used in accordance with the increase of the data transfer rate. In the transmission apparatus disclosed in Japanese Patent Laid-Open No. Hei 10-163883 mentioned above, a transmission clock signal is produced by sampling out a reference clock signal. However, in order to raise the data transfer rate with the transmission apparatus, the rate of the reference clock signal must be raised.